Current memory technologies, such as dynamic random access memory, NAND flash memory, are approaching very difficult issues related their continuous scaling to and beyond the 16nm technology generation. Research over the past 10-15 years has led to the discovery of several new memory technologies.

 

According to prediction by ITRS 2010, ferroelectric field effect transistor (FeFET) is one of the new emerging memories which are promising to be scaled down to or below 16nm technology generation. However the retention time of FeFET suffers from the poor interface between ferroelectric film and Si substrate. To solve this problem, one insulator buffer layer is offen inserted between ferroelectric film and Si to construct the metal-ferroelectric-insulator-Si (MFIS) structure. High dielectric constant buffer layer materials are required to reduce the depolarization effect, decrease the voltage drop across the buffer layer and the leakage current in the MFIS devices. In the past two decades, there is tremendous research on the high-k buffer layers for MFIS memory device applications. This presentation will summarize and review the progress on the high-k buffer layers investigated in MFIS devices. Then the issues existing for high-k materials intergration into MFIS devices are discussed, and possible solutions were suggested. Finally, our recent work on developing HfTaO and HfAlO buffer layers for MFIS FeFET applications will be demonstrated.